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nexusstc/CMOS Fractional-N Synthesizers: Design for High Spectral Purity and Monolithic Integration/ecad71728a04652926edfb663cf0709f.pdf
CMOS Fractional-N Synthesizers: Design for High Spectral Purity and Monolithic Integration (The Springer International Series in Engineering and Computer Science (724)) 🔍
Bram De Muer, Michiel Steyaert, Bram de Muer Springer, The Springer International Series in Engineering and Computer Science, 2003, 2003
英语 [en] · PDF · 15.4MB · 2003 · 📘 非小说类图书 · 🚀/lgli/lgrs/nexusstc/zlib · Save
描述
CMOS Fractional-N Synthesizers starts with a comprehensive introduction to general frequency synthesis. Different architectures and synthesizer building blocks are discussed with their relative importance on synthesizer specifications. The process of synthesizer specification derivation is illustrated with the DCS-1800 standard as a general test case.
The book tackles the design of fractional-N synthesizers in CMOS on circuit level as well as system level. The circuit level focuses on high-speed prescaler design up to 12 GHz in CMOS and on fully integrated, low-phase-noise LC-VCO design. High-Q inductor integration and simulation in CMOS is elaborated and flicker noise minimization techniques are presented, ranging from bias point choice to noise filtering techniques.
On a higher level, a systematic design strategy has been developed that trades off all noise contributions and fast dynamics for integrated capacitance (area). Moreover, a theoretical DeltaSigma phase noise analysis is presented, extended with a fast non-linear analysis method to accurately predict the influence of PLL non-linearities on the spectral purity of the DeltaSigma fractional-N frequency synthesizers.
备用文件名
lgli/ecad71728a04652926edfb663cf0709f.pdf
备用文件名
lgrsnf/ecad71728a04652926edfb663cf0709f.pdf
备用文件名
zlib/Engineering/Bram De Muer, Michiel Steyaert/CMOS Fractional-N Synthesizers: Design for High Spectral Purity and Monolithic Integration_2283808.pdf
备选作者
Bram de Muer, Bram De Muer, Michiel Steyaert
备选作者
by Bram De Muer, Michiel Steyaert
备选作者
De Muer, Bram, Steyaert, Michiel
备用出版商
Kluwer Academic Publishers ; New York
备用版本
The Kluwer international series in engineering and computer science -- 724, Boston, Massachusetts, 2003
备用版本
United States, United States of America
备用版本
Springer Nature, Boston, 2003
备用版本
Boston, United States, 2003
备用版本
1 edition, January 2003
备用版本
Boston, [Online, 2003
元数据中的注释
0
元数据中的注释
lg1114923
元数据中的注释
{"edition":"2003","isbns":["1402073879","9781402073878"],"last_page":270,"publisher":"Springer","series":"The Springer International Series in Engineering and Computer Science"}
元数据中的注释
Includes bibliographical references (p. [243]-256] and index.
备用描述
<p>CMOS Fractional-N Synthesizers starts with a comprehensive introduction to general frequency synthesis. Different architectures and synthesizer building blocks are discussed with their relative importance on synthesizer specifications. The process of synthesizer specification derivation is illustrated with the DCS-1800 standard as a general test case.</p>
<p>The book tackles the design of fractional-N synthesizers in CMOS on circuit level as well as system level. The circuit level focuses on high-speed prescaler design up to 12 GHz in CMOS and on fully integrated, low-phase-noise LC-VCO design. High-Q inductor integration and simulation in CMOS is elaborated and flicker noise minimization techniques are presented, ranging from bias point choice to noise filtering techniques.</p>
<p>On a higher level, a systematic design strategy has been developed that trades off all noise contributions and fast dynamics for integrated capacitance (area). Moreover, a theoretical DeltaSigma phase noise analysis is presented, extended with a fast non-linear analysis method to accurately predict the influence of PLL non-linearities on the spectral purity of the DeltaSigma fractional-N frequency synthesizers.</p>
备用描述
Examines the design of monolithic CMOS frequency synthesizers that can attain the highest spectral purity and fast switching with moderate power consumption, namely a DS-controlled fractional-N synthesizer. The authors (KU Leuven) first review the requirements of the frequency synthesizer in the DCS-1800 system, then develop high speed frequency dividers, high speed voltage controlled oscillators (VCOs), and a dual-path phase-locked loop (PLL) filter. The final chapter presents a monolithic 1.8 GHz DS fractional-N PLL frequency synthesizer, which may lead to an inexpensive cellular transceiver solution. Annotation (c)2003 Book News, Inc., Portland, OR (booknews.com)
备用描述
Preliminaries......Page 1
Abstract......Page 6
List of Symbols and Abbreviations......Page 8
Contents......Page 14
1 Introduction......Page 20
2 On Frequency Synthesis......Page 32
3 High-Speed CMOS Prescalers......Page 72
4 Monolithic CMOS LC-VCOs......Page 104
5 Monolithic Phase-Locked Loops......Page 156
6 A 1.8 GHz CMOS Fractional-N Frequency Synthesizer......Page 182
7 Conclusions......Page 240
A Modulators with DC-inputs......Page 248
Index......Page 252
Bibliography......Page 262
开源日期
2013-12-21
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