This book demonstrates how to use the Synopsys Sentaurus TCAD 2014 version for the design and simulation of 3D CMOS (complementary metal–oxide–semiconductor) semiconductor nanoelectronic devices, while also providing selected source codes (Technology Computer-Aided Design, TCAD). Instead of the built-in examples of Sentaurus TCAD 2014, the practical cases presented here, based on years of teaching and research experience, are used to interpret and analyze simulation results of the physical and electrical properties of designed 3D CMOSFET (metal–oxide–semiconductor field-effect transistor) nanoelectronic devices. The book also addresses in detail the fundamental theory of advanced semiconductor device design for the further simulation and analysis of electric and physical properties of semiconductor devices. The design and simulation technologies for nano-semiconductor devices explored here are more practical in nature and representative of the semiconductor industry, and as such can promote the development of pioneering semiconductor devices, semiconductor device physics, and more practically-oriented approaches to teaching and learning semiconductor engineering.  The book can be used for graduate and senior undergraduate students alike, while also offering a reference guide for engineers and experts in the semiconductor industry. Readers are expected to have some preliminary knowledge of the field.

nexusstc/3D TCAD Simulation for CMOS Nanoeletronic Devices/4b687c57d759f6fd7a378683c33e62ae.pdf

lgli/3D TCAD Simulation for CMOS Nanoeletronic Devices.pdf

lgrsnf/3D TCAD Simulation for CMOS Nanoeletronic Devices.pdf

scihub/10.1007/978-981-10-3066-6.pdf

scihub/10.1111/wej.12449.pdf

zlib/Engineering/Yung-Chun Wu, Yi-Ruei Jhan/3D TCAD Simulation for CMOS Nanoeletronic Devices_2946702.pdf

429717_Print.indd

Wu, J.; Li, S. C.; Xu, Z. H.; Zhang, L. W.

Wu, Yung-Chun, Jhan, Yi-Ruei

0002624

John Wiley and Sons; Wiley (Blackwell Publishing); Wiley-Blackwell; Wiley (ISSN 1747-6585)

John Wiley and Sons; Wiley (Blackwell Publishing); Wiley-Blackwell; Wiley (ISSN 1747-6593)

Springer Science + Business Media Singapore Pte Ltd

Springer Singapore Pte. Limited

Springer Nature (Textbooks & Major Reference Works), Singapore, 2017

Water and Environment Journal, #1, 34, pages 143-152, 2018 dec 27

1st ed. 2018, US, 2017

Singapore, Singapore

Jul 05, 2017

0

sm78119690

lg1704868

producers:
Acrobat Distiller 10.0.0 (Windows)

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Preface 5
About the book (Modify by author Yung-Chun Wu) 7
Contents 8
About the Authors 11
1 Introduction of Synopsys Sentaurus TCAD Simulation 12
1.1 Introduction 12
1.2 Introduction of Moore’s Law and FinFET 13
1.3 Sentaurus Window Environment and Workbench for TCAD Task Management 16
1.4 Synopsys Sentaurus TCAD Software and Working Environment 19
1.5 Simulation Project View on Sentaurus Workbench (SWB) 25
1.6 Sentaurus Visual 25
1.7 Calibration and Services 27
References 28
2 2D MOSFET Simulation 29
2.1 Complementary MOS (CMOS) Technology 29
2.2 [Example 2.1] 2D n-Type MOSFET with Id–Vg Characteristics Simulation 33
2.3 [Example 2.2] 2D n-Type MOSFET with Id–Vd Characteristics Simulation 61
2.4 [Example 2.3] 2D p-Type MOSFET with Id–Vg Characteristics Simulation 70
2.5 [Example 2.4] 2D p-Type MOSFET with Id–Vg Characteristics Simulation 79
2.6 [Example 2.5] 2D n-Type MOSFET with LDD (Lightly Doped Drain) Simulation 89
2.7 Summary 100
References 100
3 3D FinFET with Lg = 15 nm and Lg = 10 nm Simulation 101
3.1 Introduction of FinFET 101
3.2 Design Considerations of Threshold Voltage (Vth), Leakage Current (Ioff), and Power Consumption (Power) 105
3.3 Design Considerations of High-k Dielectric Materials and Metal Gate 108
3.4 Design Consideration of Device Gate and TCAD Design Guideline 111
3.5 FinFET 3D Simulation 114
3.5.1 Establishment of FinFET Structure 114
3.5.2 Physical Property Analysis 115
References 193
4 Inverter and SRAM of FinFET with Lg = 15 nm Simulation 194
4.1 Voltage Transfer Curve of Inverter 194
4.2 Speed of CMOS Inverter—Importance of Ion 196
4.3 CMOS Id–Vg Matching Diagram for High-Performance Transistors 197
4.4 [Example 4.1] Inverter of 3D FinFET with Lg = 15 nm 198
4.5 TCAD Simulation of Static Random-Access Memory (SRAM) 204
4.6 SRAM Operation 205
4.7 [Example 4.2] Simulation of SRAM of 3D FinFET with Lg = 15 nm 209
References 219
5 Gate-All-Around (GAA) NWFET with Lg = 10 nm Simulation 220
5.1 Introduction of Gate-All-Around Nanowire FET (GAA NWFET) 220
5.2 [Example 5.1] 3D IM n-Type GAA NWFET 223
5.3 [Example 5.2] 3D IM p-Type GAA NWFET 231
5.4 [Example 5.3] 3D Cylindrical IM n-Type GAA NWFET 236
References 245
6 Junctionless FET with Lg = 10 nm Simulation 246
6.1 Foreword 246
6.2 Short-Channel Effect (SCE) of CMOS Device 247
6.3 JL—FET Operating Mechanism 248
6.4 [Example 6.1] n-Type JL—FET with Lg = 10 nm 251
6.5 [Example 6.2] p-Type JL—FET with Lg = 10 nm 254
References 264
7 Steep Slope Tunnel FET Simulation 265
7.1 Problems Facing Conventional MOSFET 265
7.2 Operating Mechanism of Tunnel FET (TFET) 266
7.3 Example 7.1 (Design and Simulation of 3D n-Type TFET) 269
7.4 Example 7.2 (3D n-Type TFET of Different Drain Doping Concentrations) 276
7.5 Example 7.3 (3D n-Type TFET with Asymmetrical Gate) 280
7.5.1 Descriptions of Motivation and Principle 280
7.6 Summary of This Chapter 286
References 286
8 Extremely Scaled Si and Ge to Lg = 3-nm FinFETs and Lg = 1-nm Ultra-Thin Body Junctionless FET Simulation 287
8.1 Foreword 287
8.1.1 Challenges of Sub-10-nm Technology Node 288
8.1.2 Material Selection for Sub-10-nm Technology Node 288
8.2 Design Guideline of Sub-20-nm to 9-nm Gate Length Si FinFET of Wine-Bottle Channel 289
8.2.1 Device Structure and Sub-20-nm FinFET Experimental Data 289
8.2.2 Simulation Results and Discussion 289
8.3 Study of Silicon Lg = 3-nm Bulk IM, AC, and JL FinFET 291
8.4 Study of Germanium Lg = 3-nm Bulk FinFET 299
8.5 Study of Silicon and Germanium UTB-JL—FET with Ultra-Short Gate Length = 1 and 3 nm 305
References 310
Appendix: Synopsys Sentaurus TCAD 2014 Version Software Installation and Environmental Settings 312

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Erscheinungsdatum: 05.07.2017

2017-06-26