__Software Synthesis from Dataflow Graphs__ addresses the problem of generating efficient software implementations from applications specified as synchronous dataflow graphs for programmable digital signal processors (DSPs) used in embedded real- time systems. The advent of high-speed graphics workstations has made feasible the use of graphical block diagram programming environments by designers of signal processing systems. A particular subset of dataflow, called Synchronous Dataflow (SDF), has proven efficient for representing a wide class of unirate and multirate signal processing algorithms, and has been used as the basis for numerous DSP block diagram-based programming environments such as the Signal Processing Workstation from Cadence Design Systems, Inc., COSSAP from Synopsys^®^ (both commercial tools), and the Ptolemy environment from the University of California at Berkeley. A key property of the SDF model is that static schedules can be determined at compile time. This removes the overhead of dynamic scheduling and is thus useful for real-time DSP programs where throughput requirements are often severe. Another constraint that programmable DSPs for embedded systems have is the limited amount of on-chip memory. Off-chip memory is not only expensive but is also slower and increases the power consumption of the system; hence, it is imperative that programs fit in the on-chip memory whenever possible.
__Software Synthesis from Dataflow Graphs__ reviews the state-of-the-art in constructing static, memory-optimal schedules for programs expressed as SDF graphs. Code size reduction is obtained by the careful organization of loops in the target code. Data buffering is optimized by constructing the loop hierarchy in provably optimal ways for many classes of SDF graphs. The central result is a uniprocessor scheduling framework that provably synthesizes the most compact looping structures, called single appearance schedules, for a certain class of SDF graphs. In addition, algorithms and heuristics are presented that generate single appearance schedules optimized for data buffering usage. Numerous practical examples and extensive experimental data are provided to illustrate the efficacy of these techniques.

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by Shuvra S. Battacharyya, Praveen K. Murthy, Edward A. Lee

Shuvra S. Bhattacharyya; Praveen K. Murthy; Edward A. Lee

The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing -- 360, Kluwer international series in engineering and computer science -- 360., Boston, MA, Massachusetts, 1996

Softcover reprint of the original 1st ed. 1996, PT, 2011

United States, United States of America

Springer Nature, New York, NY, 2012

1, 2012

lg960378

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Front Matter....Pages i-xi
Introduction....Pages 1-27
Terminology and Notation....Pages 29-36
Synchronous dataflow....Pages 37-56
Looped Schedules....Pages 57-92
Loose Interdependence Algorithms....Pages 93-118
Joint Code and Data Minimization....Pages 119-140
Pairwise Grouping of Adjacent Nodes....Pages 141-160
Experiments....Pages 161-167
Open Issues....Pages 169-174
Back Matter....Pages 175-189

The Springer International Series in Engineering and Computer Science
Erscheinungsdatum: 05.10.2011

2013-08-01