This book describes the development of a new low-cost medium wavelength IR (MWIR) monolithic imager technology for high-speed uncooled industrial applications. It takes the baton on the latest technological advances in the field of vapor phase deposition (VPD) PbSe-based MWIR detection accomplished by the industrial partner NIT S.L., adding fundamental knowledge on the investigation of novel VLSI analog and mixed-signal design techniques at circuit and system levels for the development of the readout integrated device attached to the detector. In order to fulfill the operational requirements of VPD PbSe, this work proposes null inter-pixel crosstalk vision sensor architectures based on a digital-only focal plane array (FPA) of configurable pixel sensors. Each digital pixel sensor (DPS) cell is equipped with fast communication modules, self-biasing, offset cancellation, analog-to-digital converter (ADC) and fixed pattern noise (FPN) correction. In-pixel power consumption is minimized by the use of comprehensive MOSFET subthreshold operation.

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Low-power cmos digital-pixel imagers for high -speed uncooled pbse ir applications

Margarit, Josep Maria

Springer Nature Switzerland AG

Springer theses, 1ST ed. 2017, Place of publication not identified, 2017

Springer Theses, Recognizing Outstanding Ph. D. Research, Cham, 2017

Springer Nature, Cham, Switzerland, 2017

Springer theses, Cham, Switzerland, 2017

Switzerland, Switzerland

Springer Theses, 2016

1st ed. 2017, 2016

sm63417026

producers:
Acrobat Distiller 10.0.0 (Windows)

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Supervisors’ Foreword 7
Parts of this thesis have been published in the following articles: 9
Acknowledgements 11
Contents 13
About the Author 16
Acronyms 17
1 Introduction 20
1.1 Seeing Beyond the Visible 20
1.1.1 Vision Cameras 20
1.1.2 Seizing the Red End 22
1.2 Common Metrics and Figures of Merit 24
1.3 IR Direct Detectors 28
1.3.1 Thermal and Photonic Transduction 28
1.3.2 IR Detection Today 31
1.4 Uncooled PbSe Photoconductive Technology 31
1.4.1 Detection Basis 31
1.4.2 Device Performance 33
1.4.3 Electrical Model 36
1.5 CMOS IR Imagers 37
1.5.1 Readout Techniques 37
1.5.2 FPA Architectures 40
1.5.3 State-of-the-Art IR Vision Sensors 42
1.6 Objectives and Scope 44
1.6.1 Motivation 44
1.6.2 R&D Context 45
1.6.3 Working Hypothesis 46
1.6.4 The Challenges 47
1.6.5 Methodology and Contents 49
References 51
2 Frame-Based Smart IR Imagers 57
2.1 Imager Architecture and Operation Proposal 57
2.2 All-Digital Program-In and Read-Out Interface 60
2.2.1 Motivation and Design Proposal 60
2.2.2 Compact CMOS Implementation 63
2.3 Input Signal Conditioning 66
2.3.1 Motivation and Design Proposal 66
2.3.2 Compact CMOS Implementation 67
2.4 Asynchronous ADC with CDS 73
2.4.1 Motivation and Design Proposal 73
2.4.2 Compact CMOS Implementation 76
2.5 Individual Gain Tuning 83
2.5.1 Motivation and Design Proposal 83
2.5.2 Compact CMOS Implementation 84
2.6 Local Bias Generation 85
2.6.1 Motivation and Design Proposal 85
2.6.2 Compact CMOS Implementation 87
References 89
3 Frame-Free Compact-Pitch IR Imagers 91
3.1 Imager Architecture and Operation Proposal 91
3.2 Event-Driven Communications 93
3.2.1 Motivation and Design Proposal 93
3.2.2 In-Pixel Compact CMOS Implementation 97
3.3 Self-biasing and Temporal-Difference Filtering 98
3.3.1 Motivation and Design Proposal 99
3.3.2 Compact CMOS Implementation 100
3.4 Digital Contrast Tuning 104
3.4.1 Motivation and Design Proposal 104
3.4.2 Compact CMOS Implementation 105
3.5 Reset-Insensitive Spike-Counting ADC 107
3.5.1 Motivation and Design Proposal 107
3.5.2 Compact CMOS Implementation 110
3.6 Fair AE Arbitration 112
3.6.1 Motivation and Design Proposal 112
3.6.2 Compact CMOS Implementation 114
References 116
4 Pixel Test Chips in 0.35- and 0.15-μm CMOS Technologies 118
4.1 A 100μm-Pitch Smart Pixel with Offset Auto-Calibration ƒ 118
4.1.1 Full-Custom ASIC Design 119
4.1.2 Experimental Results 123
4.2 A 200 and 130μm-Pitch Smart Pixel with Full Programmability 133
4.2.1 Full-Custom ASIC Designs 133
4.2.2 Experimental Results 141
4.3 A Self-biased 45μm-Pitch AER Pixel with Temporal Difference Filtering 144
4.3.1 Full-Custom ASIC Design 144
4.3.2 Experimental Results 149
References 151
5 Imager Test Chips in 2.5-, 0.35- and 0.15-m CMOS Technologies 152
5.1 A Low-Cost 32times32 Integrated Test Platform for Electrical Characterization ƒ 152
5.1.1 Full-Custom ASIC Design 157
5.1.2 Experimental Results 162
5.2 An 80times80 Sub-1W/pix 2kfps Smart MWIR Imager 165
5.2.1 Monolithic PbSe-CMOS Integration 166
5.2.2 Experimental Results 169
5.3 A 32times32 Frame-Free Compact-Pitch MWIR Imager 177
5.3.1 Full-Custom ASIC Design 178
5.3.2 Experimental Results 178
5.4 Comparison with State-of-the-Art IR Imagers 180
References 184
6 Conclusions 186
6.1 Contributions 186
6.2 Discussion and Future Work 189
Reference 190

Front Matter....Pages i-xxi
Introduction....Pages 1-37
Frame-Based Smart IR Imagers....Pages 39-72
Frame-Free Compact-Pitch IR Imagers....Pages 73-99
Pixel Test Chips in 0.35- and 0.15- \(\,\upmu \) m CMOS Technologies....Pages 101-134
Imager Test Chips in 2.5-, 0.35- and 0.15- \(\upmu \) m CMOS Technologies....Pages 135-168
Conclusions....Pages 169-173

2017-02-20